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E2U0060-18-84
Semiconductor MSM7731-01
Semiconductor Multifunction PCM CODEC (Voice Signal Processor)
This version: Aug. 1998 MSM7731-01
Pr el im in ar y
GENERAL DESCRIPTION
The MSM7731 is an LSI device developed for portable, handsfree communication with built-in line echo canceler, acoustic echo canceler, and transmission signal noise canceler. Built-in to the voice signal interface is a linear CODEC for the analog interface on the acoustic-side, and a linear CODEC for the analog interface on the line-side. On the line-side, in addition to the analog interface, there is also a m-law PCM/16-bit linear digital interface. Equipped with gain and mute controls for data transmission and reception, a m-law PCM/16bit linear digital interface for memo recording and message output, and transfer clock and sync clock generators for digital communication, this device is ideally suited for a handsfree system.
FEATURES
* Single 3 V power supply operation (2.7 V to 3.6 V) * Built-in 2-channel (line and acoustic) echo canceler Echo attenuation : 35 dB (typ.) Cancelable echo delay time : Line echo canceler + acoustic echo canceler : Tlined = 27 ms (max.), Tacoud = 59 ms - Tlined (max.) Acoustic echo canceler only : Tacoud = 59 ms (max.) * Built-in transmission signal noise canceler Noise attenuation: 13 dB (typ.) for white noise 40 dB (typ.) for single tone * Built-in 2-channel CODEC Synchronous transmission and reception enables full duplex operation * Built-in analog input gain amp stage (max. gain = 30 dB) * Analog output configuration: Push-pull drive (can drive a 1.2 kW load) * Built-in transmit slope filter * Digital interface coding formats: m-law PCM, 16-bit linear (2's complement) * Digital interface sync formats: Normal-sync, short-frame-sync * Built-in digital transmission clock generators Sync clock (SYNC): 8 kHz output Transmission clock (BCLK): 64 kHz output (m-law PCM)/128 kHz output (16-bit linear) * Digital transmission rate External input: 64 kbps to 2048 kbps Internal generation: 64 kbps (m-law PCM)/128 kbps (16-bit linear) * Fixed digital interface sync clock (SYNC) enables automatic power-down * Master clock frequency: 19.2 MHz Compatible with crystal oscillator and crystal * Low power consumption Operating mode: typ. 105mW (when VDD = 3.0 V) Power-down mode: typ. 0.3mW (when VDD = 3.0 V) * Control by both the serial microcomputer interface and parallel port is possible * Transmit/receive mute function, transmit/receive programmable gain setting * Package: 64-pin plastic QFP (QFP64-P-1414-0.80-BK) (Product name: MSM7731-01GA) 1/43
Semiconductor
BLOCK DIAGRAM
Linear CODEC (Acoustic side)
BPF
Acoustic Echo Canceler
SinA STTsA LPADA SoutA GPADA Noise Canceler Slope Filter TPAD RinL Acoustic Adaptive FIR Filter (AAFF)
Line Echo Canceler
RoutL ATTrL GainL
Linear CODEC (Line side)
LPF
+ -+
Center Clip
LPWI
- + 1.2kW
AIN
AGSX
AVFRO APWI
- + 1.2kW
AOUT
SG
Clock Gen
+ -
ADC
DAC Power Calc. Howling Detector Double Talk Det RC LPF
LOUT LVFRO
RC LPF
RC LPF
Power Calc. Howling Detector Double Talk Det
Line Adaptive FIR Filter (LAFF)
RC LPF
LGSX
- +
DAC GPADL LPF RoutA GainA ATTrA RinA RPAD Center Clip ATTsL SoutL SinL
ADC
LIN
+
- ++
LPADL
+
BPF
VREF Timing Gen AEC Controller P/S & S/P EC/NC/SF/PAD Controller MCU Interface LEC Controller P/S & S/P
LINEEN
MSM7731-01
PDN/RST MCK/X1 X2
SYNC SYNCSEL BCLK CLKSEL PCMSEL
ATHR AGC AATT AHLD AHD
PCMEO PCMEI
RPAD1-4 TPAD1-4 ECSEL GLPADTHR NCTHR SLPTHR RST
DEN EXCK DIN DOUT MCUSEL
LTHR LGC LATT LHLD LHD
PCMO PCMI
AGND AVDD DGND1, 2 DVDD1, 2 TEST1-4, 8 TEST9
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PIN CONFIGURATION (TOP VIEW)
ECSEL MCUSEL AHD AHLD AATT AGC DGND1 ATHR LHD
LHLD 10 LATT 11 LGC 12 LTHR 13 RPAD4 14 DVDD1 15 RPAD3 16
,
61 SLPTHR 62 NCTHR 60 TEST1 59 TEST2 64 EXCK 63 DIN 1 2 3 4 5 6 7 8 9 RPAD2 17 RPAD1 18 DGND2 19 TPAD4 20 TPAD3 21 TPAD2 22
MSM7731-01
55 PDN/RST
51 CLKSEL
49 PCMEI 48 PCMEO 47 PCMO 46 PCMSEL 45 SYNCSEL 44 DOUT 43 DEN 42 DVDD2 41 GLPADTHR 40 TEST9 39 LINEEN 38 AGND 37 LOUT 36 LPWI 35 LVFRO 34 LGSX 33 LIN SG 32
58 TEST3
57 TEST4
56 TEST8
53 SYNC
52 BCLK AVFRO 29
TPAD1 23
MCK/X1 24
X2 25
AVDD 26
AGSX 27
AIN 28
APWI 30
64-Pin Plastic QFP
AOUT 31
50 PCMI
54 RST
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PIN DESCRIPTIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol ECSEL MCUSEL AHD AHLD AATT AGC DGND1 ATHR LHD LHLD LATT LGC LTHR RPAD4 DVDD1 RPAD3 RPAD2 RPAD1 DGND2 TPAD4 TPAD3 TPAD2 TPAD1 MCK/X1 X2 AVDD AGSX AIN AVFRO APWI AOUT SG Type I I I I I I I I I I I I I I I I I I I I I I I I O I O I O I O O Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol LIN LGSX LVFRO LPWI LOUT AGND LINEEN TEST9 GLPADTHR DVDD2 DEN DOUT SYNCSEL PCMSEL PCMO PCMEO PCMEI PCMI CLKSEL BCLK SYNC RST PDN/RST TEST8 TEST4 TEST3 TEST2 TEST1 SLPTHR NCTHR DIN EXCK Type I O O I O I I O I I I O I I O O I I I I/O I/O I I I I I I I I I I I
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PIN FUNCTIONAL DESCRIPTION
AIN, AGSX These are the acoustic analog input and level adjusting pins. The AIN pin is connected to the inverting input of the internal amp and the AGSX pin is connected to the amp output. For level adjustment, refer to the diagram below (Figure 1). At power-down reset, the AGSX pin goes to a high impedance state. AVFRO, AOUT, APWI These are the acoustic analog output and level adjusting pins. The AVFRO pin is an audio output and can directly drive 20 kW. The AOUT pin is an analog output and can directly drive a load of 1.2 kW. For level adjustment, refer to the diagram below (Figure 1). At power-down reset, these output pins go to a high impedance state. LIN, LGSX These are the line analog input and level adjusting pins. The LIN pin is connected to the inverting input of the internal amp and the LGSX pin is connected to the amp output. For level adjustment, refer to the diagram below (Figure 1). At power-down reset, the LGSX pin goes to a high impedance state. If LIN is not used, short the LIN and LGSX pins together. LVFRO, LOUT, LPWI These are the line analog output and level adjusting pins. The LVFRO pin is an audio output and can directly drive 20 kW. The LOUT pin is an analog output and can directly drive a load of 1.2 kW. For level adjustment, refer to the diagram below (Figure 1). At power-down reset, these output pins go to a high impedance state. If LOUT is not used, short the LPWI and LOUT pins together. LINEEN This is the power-down control pin for the line CODEC. A logic "0" continues normal operation and a logic "1" powers down only the line CODEC. If the line CODEC is not used, power down the line CODEC and short the LIN pin to the LGSX pin and the LPWI pin to the LOUT pin. This procedure results in the low consumption of electrical power. At power-down, the output pins go to a high impedance state. Since this pin is ORed with CR0-B5 of the control register, set the pin to a logic "0" when controlling power-down by the control register. If the pin setting is changed, reset must be activated by either the PDN/RST pin or the PDN/RST bit (CR0-B7).
VAGSX/VI=R2/R1 30 R220kW Microphone VI C1 R1 R2 AGSX
Acoustic CODEC
Line CODEC
LGSX
AIN SG
- +
to ENCODER
LIN
VREF
+ - 10mF R3 APWI C2 Speaker VO Speaker amp VO/VAVFRO=R3/R4 R320kW R4 AVFRO from DECODER LPWI - + LVFRO
Same as the acoustic analog interface
0.1mF
AOUT
LOUT LINEEN
Reception signal Line side (portable phone) Transmission signal
Acoustic side (microphone, speaker)
Figure 1 Analog Interface 5/43
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MSM7731-01
SG This is the output pin for the analog signal ground potential. The output voltage is approximately 1.4 V. Insert 10 mF and 0.1 mF ceramic bypass capacitors between the AGND and SG pins. At power-down reset, this output becomes 0 V. PDN/RST This is the power-down reset control input pin. If a logic "0" is input to this pin, the device enters the power-down state. At this time, all control register bits and internal variables will be reset. After the power-down reset state is released, the device enters the initial mode (refer to the CR0 control register description). During normal operation, set this pin to a logic "1". Since the PDN/RST pin is ORed (negative logic) with CR0-B7 of the control register, set the pin to a logic "1" when controlling power-down reset by the control register. MCK/X1 This is the master clock input pin. The clock frequency is 19.2 MHz. The input clock may be asynchronous with respect to the SYNC signal or the BCLK signal. Refer to Figure 2 (a) for an example application of an external clock and Figure 2 (b) for an example oscillator circuit. X2 This is the crystal oscillator output pin. If an existing external clock is to be used, leave this pin open and input the clock to the MCK pin. Refer to Figure 2 (b) for an example oscillator circuit.
MCK/X1
X2
MCK/X1 R Crystal
X2
R : T.B.D C : T.B.D Crystal : 19.2 MHz C
C
Figure 2 (a) External Clock Application Example
Figure 2 (b) Oscillator Circuit Example
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SYNC This is the 8 kHz sync signal I/O pin for digital data communication. This pin is switched to function as an input or output by the CLKSEL pin. If the internal clock mode is selected by the CLKSEL pin, an 8 kHz clock synchronized to the BCLK signal is output and digital data communication is performed. If the external clock mode is selected by the CLKSEL pin, this pin becomes an input that requires an 8 kHz clock input synchronized to the BCLK pin, and digital data communication is performed based on this input clock. Fixing this signal to a logic "1" or logic "0" causes this device to internally write a logic "1" to the PDN/RST (CR0-B7) bit of the control register, and to enter the power-down reset state. This automatic power-down control is valid when external clock mode is selected by the CLKSEL pin and automatic power-down control has been turned ON by the SYPDN (CR11-B0) bit of the control register. BCLK This is the shift clock I/O pin for digital data communication. This pin is switched to function as an input or output by the CLKSEL pin. If the internal clock mode is selected by the CLKSEL pin, a 64 kHz or 128 kHz clock synchronized to the SYNC signal is output and digital data communication is performed. Switching between 64 kHz and 128 kHz is performed by the PCMSEL pin. If m-law PCM is selected by the PCMSEL pin, a 64 kHz clock is output. Or, if 16bit linear mode is selected, a 128 kHz clock is output. If the external clock mode is selected by the CLKSEL pin, this pin becomes an input that requires a clock input synchronized to the SYNC. In this case, the clock frequency range is from 64 kHz to 2048 kHz. CLKSEL This pin selects internal or external clock modes for the SYNC and BCLK signals. A logic "0" selects the internal clock mode. At this time, SYNC and BCLK pins are configured as output pins and each internally generated clock is output to perform digital data communication. A logic "1" selects the external clock mode and configures the SYNC and BCLK pins as input pins. At this time, digital data communication is performed with the externally input SYNC and BCLK clocks. If digital data communication is not used, set this pin to a logic "0" to select internal clocks. If the pin setting is changed, reset must be activated by either the PDN/RST pin or the PDN/RST bit (CR0-B7). PCMI This is the digital receive signal input pin on the line-side. This input signal is shifted at the rising edge of the BCLK signal and input. The beginning of digital data is identified on the rising edge of the SYNC signal. The coding format can be selected as m-law PCM or 16-bit linear (2's complement) by the PCMSEL pin. If the PCMI pin is not used, set it to a logic "1" if m-law PCM has been selected, or a logic "0" if 16-bit linear mode has been selected. The sync format can be selected as normal-sync or short-frame-sync by the SYNCSEL pin. Refer to Figure 3 for the timing. This digital input signal is added internally to the CODEC digital output signal. Be careful of overflow when using the CODEC. PCMO This is the digital transmit signal output pin on the line-side. This output signal is synchronized to the rising edge of the BCLK and SYNC signals and then output. When not used for output, this pin is in the high impedance state. It is also at high impedance during the power-down reset and the initial modes. The coding format can be selected as m-law PCM or 16-bit linear (2's complement) by the PCMSEL pin. The sync format can be selected as normal-sync or shortframe-sync by the SYNCSEL pin. Refer to Figure 3 for the timing.
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PCMEI This is the message signal input pin. Use this pin when a message is output to the speaker on the acoustic-side. This input signal is shifted at the rising edge of the BCLK signal and then input. The beginning of digital data is identified on the rising edge of the SYNC signal. The coding format can be selected as m-law PCM or 16-bit linear (2's complement) by the PCMSEL pin. If the PCMEI pin is not used, set it to a logic "1" if m-law PCM has been selected, or a logic "0" if 16-bit linear mode has been selected. The sync format can be selected as normal-sync or short-frame sync by the SYNCSEL pin. Timing is the same as for the PCMI pin (refer to Figure 3). This digital input signal is added internally to the echo canceler output signal. Be careful of overflow during telephone conversations. PCMEO This output pin is for memo recording. Use it with the memo function. This output signal is synchronized to the rising edge of the BCLK and SYNC signals and then output. When not used for output, this pin is in the high impedance state. It is also at high impedance during the powerdown reset and the initial modes. The coding format can be selected as m-law PCM or 16-bit linear (2's complement) by the PCMSEL pin. The sync format can be selected as normal-sync or short-frame-sync by the SYNCSEL pin. Timing is the same as for the PCMO pin (refer to Figure 3). SYNCSEL This is the sync timing selection pin for digital data communication. A logic "0" selects normal-sync timing and a logic "1" selects short-frame-sync timing. Refer to Figure 3 for the timing. If the pin setting is changed, reset must be activated by either the PDN/RST pin or the PDN/RST bit (CR0-B7). PCMSEL This is the coding format selection pin for digital data communication. A logic "1" selects m-law PCM and a logic "0" selects 16-bit linear (2's complement) coding format. When an internal clock is selected, the BCLK signal determines the output clock frequency. If the digital interface is not used, set this pin to logic "0" to select 16-bit linear coding format. Since this pin is logically ORed with the PCMSEL bit (CR11-B1), set the pin to a logic "0" when controlling by the control register. If the pin setting is changed, reset must be performed by either the PDN/RST pin or the PDN/ RST bit (CR0-B7).
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SYNC BCLK PCMI PCMEI D15 D14 D13 D12 D2 D2 D1 D1 D0 D0 Hi-Z D15 D14 D15 D14
PCMO PCMEO D15 D14 D13 D12
(a) 16-bit linear coding format timing (normal sync)
SYNC BCLK PCMI PCMEI PCMO PCMEO D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Hi-Z D7 D7 D6 D6
(b) m-law PCM coding format timing (normal sync)
SYNC BCLK PCMI PCMEI PCMO PCMEO Hi-Z D15 D14 D13 D15 D14 D13 D3 D3 D2 D2 D1 D1 D0 D0 Hi-Z D15 D15
(c) 16-bit linear coding format timing (short-frame sync)
SYNC BCLK PCMI PCMEI PCMO PCMEO Hi-Z D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Hi-Z D7 D7
(c) m-law PCM coding format timing (short-frame sync)
Figure 3 Digital Interface Timing
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ECSEL This is the echo canceler mode selection pin. A logic "1" selects the single echo canceler mode and a logic "0" selects the dual echo canceler mode. Since this pin is ORed with the CR0-B0 bit of the control register, set the pin to a logic "0" when controlling by the control register. If the pin setting is changed, reset must be activated by either the PDN/RST pin or the PDN/RST bit (CR0-B7). If the single echo canceler mode is selected, echo canceler control on the line-side is unnecessary. LTHR/ATHR This is the "through mode" control pin for the echo canceler. In the "through mode", SinL/A and RinL/A data is directly output to SoutL/A and RoutL/A respectively while each respective echo coefficient is maintained. A logic "0" selects the normal mode (echo canceler operation) and a logic "1" selects the "through mode." Since this pin is ORed with the CR4-B7 and CR5-B7 bits of the control register, set the pin to a logic "0" when controlling the "through mode" by the control register. Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250 ms or longer. For further details, refer to the electrical characteristics. LHD/AHD This pin turns ON or OFF the function to detect and cancel the howling that occurs in an acoustic system such as a handsfree communication system. A logic "0" turns the function ON and a logic "1" turns the function OFF. Since this pin is ORed with the CR4-B4 and CR5-B4 bits of the control register, set the pin to a logic "0" when controlling by the control register. Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250 ms or longer. For further details, refer to the electrical characteristics. LHLD/AHLD This pin controls the updating of adaptive FIR filter coefficients for the echo canceler. A logic "0" selects the normal mode (coefficient updating) and a logic "1" selects the fixed coefficient mode. Since this pin is ORed with the CR4-B2 and CR5-B2 bits of the control register, set the pin to a logic "0" when controlling by the control registers. Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250 ms or longer. For further details, refer to the electrical characteristics. LATT/AATT This pin turns ON or OFF the ATT function to prevent howling by means of attenuators (ATTsL/A, ATTrL/A) provided in the RinL/A inputs and SoutL/A outputs of the echo canceler. If input is only to RinL/A, the ATTsL/A for SoutL/A is activated. If input is only to SinL/A, or if there is input to both SinL/A and RinL/A, the ATTrL/A for RinL/A input is activated. The ATT value of each attenuator is approximately 6 dB. A logic "0" turns ON and a logic "1" turns OFF the ATT function. Since this pin setting is logically ORed with the CR4B1 and CR5-B1 bits of the control register, set the pin to a logic "0" when controlling by the control register. Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250 ms or longer. For further details, refer to the electrical characteristics.
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LGC/AGC This pin turns ON or OFF the gain control function to control the input level and prevent howling by means of gain controls (GainL/A) provided in the RinL/A inputs of the echo canceler. The gain controller adjusts the RIN input level when it is -10 dBm0 or above, and it has the control range of 0 to -8.5 dB. A logic "0" turns the function ON and a logic "1" turns the function OFF. Since this pin is ORed with the CR4-B0 and CR5-B0 bits of the control register, set the pin to a logic "0" when controlling by the control register. Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250 ms or longer. For further details, refer to the electrical characteristics. Notes: Lxx/Axx: In the above, Lxx refers to line echo canceler control pins and Axx to acoustic echo canceler control pins. xxL/xxA: In the above pin descriptions, xxL refers to line echo canceler functions and xxA to acoustic echo canceler functions. GLPADTHR This is the mode control pin for the attenuators (LPADL/A) provided in the SinL/A inputs and the amplifiers (GPADL/A) provided in the SoutL/A outputs of the echo canceler. A logic "0" selects the "through mode" and a logic "1" selects the normal mode (PAD operation). The levels are set by the CR10 register. Settings of 18, 12, 6 and 0 dB are possible. The default setting is 12 dB. If the echo return loss (value of returned echo) is amplified, set the LPAD level such that echo return loss will be attenuated. It is recommended to set the GPAD level to the positive level equal to the LPAD level. Since this pin is ORed with the CR1-B2 bit of the control register, set the pin to a logic "0" when controlling by the control register. Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250 ms or longer. For further details, refer to the electrical characteristics. NCTHR This is the noise canceler "through mode" control pin. In the "through mode" the noise canceler is halted and data is directly output. A logic "0" selects the normal mode (noise canceler operation) and a logic "1" selects the "through mode". Since this pin is ORed with the CR1-B0 bit of the control register, set the pin to a logic "0" when controlling by the control register. Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250 ms or longer. For further details, refer to the electrical characteristics. When this pin is changed from normal mode to "through mode", approximately 20 ms of data dropout will occur. SLPTHR This is the "through mode" control pin for the transmit slope filter. In the "through mode", the filter is halted and data is directly output. A logic "0" selects the normal mode (slope filter operation) and a logic "1" selects the "through mode". Since this pin is ORed with the CR1-B1 bit of the control register, set the pin to a logic "0" when controlling by the control register. Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250 ms or longer. For further details, refer to the electrical characteristics.
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RST This input pin resets coefficients of the echo canceler and noise canceler. A logic "0" causes the reset state to be entered. At this time, the filter coefficients for the echo canceler and noise canceler are reset. Control register contents are preserved. While reset is being processed, there is no sound. During normal operation, set this pin to a logic "1". Since this pin is ORed (negative logic) with the CR0-B6 bit of the control register, set the pin to a logic "1" when controlling by the control register. Use this pin in cases where the echo path changes (due to line switching during a telephone conversation, etc.), or when resuming telephone communication. Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250 ms or longer. For further details, refer to the electrical characteristics. DEN, EXCK, DIN, DOUT This is the serial port for the microcomputer interface. 13 bytes of control registers are provided in this LSI device. These pins are used to write and read data from an external microcomputer. The DEN pin is an enable signal input pin, the EXCK pin is a clock signal input pin for data shifting, the DIN pin is an address and data input pin, and the DOUT pin is a data output pin. If the microcomputer interface is not used, set the DEN pin to a logic "1" and the EXCK and DIN pins to a logic "0". In addition, use the MCUSEL pin to specify the "unused" setting of the microcomputer interface. Figure 4 shows the input timing. MCUSEL This pin selects whether the microcomputer interface is used or unused. A logic "0" specifies that the microcomputer interface is used and a logic "1" specifies that it is not used. If the microcomputer interface is not used, this pin must be set to a logic "1". This pin is ORed with the CR0-B1 bit of the control register.
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DEN EXCK DIN DOUT 1 W 2 A6 3 A5 4 A4 5 A3 A2 6 A1 7 A0 Hi-Z 8 9 B7 10 B6 11 B5 12 B4 13 B3 14 B2 15 B1 16 B0
(a) Data Write Timing 1 (8-Bit MCU)
DEN EXCK DIN DOUT 1 W 2 A6 3 A5 4 A4 5 A3 A2 6 A1 7 8 A0 9 B7 Hi-Z 10 B6 11 B5 12 B4 13 B3 14 B2 15 B1 16 B0
(b) Data Write Timing 2 (16-Bit MCU)
DEN EXCK DIN DOUT R 1 2 A6 3 A5 4 A4 5 A3 Hi-Z A2 6 A1 7 A0 B7 B6 B5 B4 B3 B2 B1 B0 Hi-Z 8 9 10 11 12 13 14 15 16
(c) Data Read Timing 1 (8-Bit MCU)
DEN EXCK DIN DOUT R 1 2 A6 3 A5 4 A4 Hi-Z 5 A3 A2 6 A1 7 A0 B7 B6 B5 B4 B3 B2 B1 B0 Hi-Z 8 9 10 11 12 13 14 15 16
(d) Data Read Timing 2 (16-Bit MCU)
Figure 4 Microcomputer Interface I/O Timing
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RPAD4, RPAD3, RPAD2, RPAD1 These are the receive signal gain adjusting and mute setting pins. Refer to Table 1 for the settings. Set these pins to a logic "0" when controlling by the control register. Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250 ms or longer. For further details, refer to the electrical characteristics. TPAD4, TPAD3, TPAD2, TPAD1 These are the transmit signal gain adjusting and mute setting pins. Refer to Table 1 for the settings. Set these pins to a logic "0" when controlling by the control register. Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250 ms or longer. For further details, refer to the electrical characteristics.
Table 1 RPAD/TPAD Settings
RPAD4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RPAD3 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 RPAD2 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 RPAD1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 TPAD4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 TPAD3 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 TPAD2 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 TPAD1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Level 21 dB 18 dB 15 dB 12 dB 9 dB 6 dB 3 dB 0 dB -3 dB -6 dB -9 dB -12 dB -15 dB -18 dB -21 dB MUTE
TEST1-4, 8 Test inputs. Set these pins to a logic "0". TEST9 Test output.
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ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Digital Input Voltage Digital Output Voltage Storage Temperature Symbol VDD VDIN VOUT TSTG Condition -- -- -- -- Rating -0.3 to +5.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -55 to +150 Unit V V V C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply voltage Operating Temperature Input High Voltage Symbol VDD Ta VIH Condition -- -- SYNC, BCLK input pins MCK/X1 input pin Other digital input pins Input Low Voltage Digital Input Rise Time Digital Input Fall Time Master Clock Frequency Master Clock Duty Ratio Bit Clock Frequency Bit Clock Duty Ratio Synchronous Signal Frequency Synchronous Signal Width Transmit/Receive Sync Signal Setting Time Digital Output Load VIL tIR tIf FMCK DMCK FBCK DCK FSYNC tWS tBS tSB RDL CDL1 CDL2 Bypass Capacitor for SG CSG MCK/X1 input pin Other digital input pins All digital inputs All digital inputs MCK/X1 MCK/X1 BCLK (during input) BCLK (during input) SYNC (during input) SYNC (during input) BCLK to SYNC (during input) SYNC to BCLK (during input) DOUT, PCMO, PCMEO DOUT, PCMO, PCMEO SYNC, BCLK (during output) SG to AG Min. 2.7 -40 0.5VDD 0.65VDD 0.45VDD 0 -- -- -100 ppm 40 64 40 -100 ppm 1 BCLK 100 100 1 -- -- 10+0.1 -- -- -- +19.2 50 -- 50 8 -- -- -- -- -- -- -- 0.35VDD 0.16VDD 20 20 60 2048 60 100 -- -- -- 50 20 -- V ns ns % kHz % ms ns ns kW pF pF mF -- VDD V Typ. -- +25 Max. 3.6 +85 Unit V C
+100 ppm MHz
+100 ppm kHz
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ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(VDD = 2.7 V to 3.6 V Ta = -25C to +70C) Parameter Power Supply Current 1 Power Supply Current 2 Input Leakage Current High Level Digital Output Voltage Low Level Digital Output Voltage Digital Output Leakage Current Input Capacitance Symbol IDD1 IDD2 IIH IIL VOH VOL IO CIN Condition Operating, no signal (VDD = 3.0 V)
Power down mode (VDD = 3.0 V, MCK = 0 V)
Min. -- -- -- -- 0.5VDD 0 -- --
Typ. 35 0.1 -- -- -- 0.2 -- 5
Max. 45 1 2 2 VDD 0.4 10 --
Unit mA mA mA mA V V mA pF
VI = VDD VI = 0 V IOH = 0.4 mA IOL = 3.2 mA DOUT, PCMO, PCMEO --
Analog Interface
(VDD = 2.7 V to 3.6 V Ta = -25C to +70C) Parameter Input Resistance Output Load Resistance Symbol RINA RINL RLA1 RLA2 RLL1 RLL2 Output Load Capacitance Output Voltage Level (*1) CLA1 CLL1 VOA1 VOA2 VOL1 VOL2 Offset Voltage VOFA1 VOFA2 VOFL1 VOFL2 SG Output Voltage SG Output Impedance VSG RSG AIN, APWI LIN, LPWI
AGSX, AVFRO
Condition
Min. 10 10 20 1.2 20 1.2 -- -- RL = 20 kW RL = 1.2 kW RL = 20 kW RL = 1.2 kW -- -- -- -- -100 -20 -100 -20 -- --
Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.4 40
Max. -- -- -- -- -- -- 100 100 1.3 2.6 1.3 2.6 +100 +20 +100 +20 -- 80
Unit MW MW kW kW kW kW pF pF Vpp Vpp Vpp Vpp mV mV mV mV V kW
AOUT LGSX, LVFRO LOUT AGSX, AVFRO, AOUT LGSX, LVFRO, LOUT AGSX, AVFRO AOUT LGSX, LVFRO LOUT AVFRO AOUT AVFRO LOUT SG SG
*1 0.320 Vrms = 0 dBm0, +3.14 dBm0 = 1.30 Vpp
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Semiconductor Digital Interface
MSM7731-01
(VDD = 2.7 V to 3.6 V Ta = -25C to +70C) Parameter Power-down Reset Signal Pulse Width Power-down Reset Start Time Power-down Reset End Time Control Pulse Width Control Start Time Control End Time Bit Clock Frequency Bit Clock Duty Ratio Synchronous Signal Frequency Sync Signal Duty Ratio Transmit/Receive Sync Signal Setting Time Input Setup Time Input Hold Time Digital Output Delay Time tPDND tPDNH tPARW tPARD tPARH FBCK DCK FSYNC tBS tSB tDS tDH tSDX tXD1 tXD2 tXD3 MCU Interface Digital Input/Output Setting Timing tM1 tM2 tM3 tM4 tM5 tM6 tM7 tM8 tM9 tM10 tM11 EXCK Clock Frequency fECK RDL = 1 kW, CDL = 20 pF RDL = 1 kW, CDL = 20 pF CDL = 20 pF (output mode, PCM) CDL = 20 pF (output mode, linear) CDL = 20 pF (output mode) CDL = 20 pF (output mode) BCLK to SYNC (output mode) SYNC to BCLK (output mode) -- -- RDL = 1 kW, CDL = 50 pF RDL = 1 kW, CDL = 50 pF RDL = 1 kW, CDL = 50 pF RDL = 1 kW, CDL = 50 pF Symbol tRSTW Condition PDN/RST pin PDN/RST control bit
PDN/RST pin and PDN/RST control bit PDN/RST pin and PDN/RST control bit
Min. 1 1.6 -- -- 140 250 -- -- -- -- 40 -- 40 100 100 100 100 -- -- -- -- 20 20 50 100 50 50 -- 0 50 -- 100 --
Typ. -- -- -- -- -- -- -- 64 128 50 8 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max. -- 50 180 -- 250 250 -- -- 60 -- 60 -- -- -- -- 100 100 100 100 -- -- -- -- -- -- 30 -- -- 30 -- 10
Unit ms ns ms ms ms ms kHz kHz % kHz % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
200+a (*2) ms
Power-down Reset Internal Setting Time tPDNS
SYNC pin (input mode) (*3)
DSYNC CDL = 20 pF (output mode)
*2 a : Crystal activation time *3 Applies to the following pins/control bits: LINEEN, SLPTHR, NCTHR, GLPADTHR, TPAD6-1, RPAD6-1, RST, ATHR, AATT, AHLD, AHD, AGC, LTHR, LATT, LHLD, LHD, and LGC
17/43
Semiconductor AC Characteristics (Line CODEC/Acoustic CODEC)
MSM7731-01
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Condition Parameter Symbol LOSS T1 Transmit Frequency Response LOSS T3 LOSS T4 LOSS T5 LOSS T6 LOSS R1 Receive Frequency Response LOSS R2 LOSS R3 LOSS R4 LOSS R5 SD T1 Transmit Signal to Distortion Ratio SD T2 SD T3 SD T4 SD T5 SD R1 Receive Signal to Distortion Ratio SD R2 SD R3 SD R4 SD R5 GT T1 Transmit Gain Tracking GT T2 GT T3 GT T4 GT T5 GT R1 Receive Gain Tracking GT R2 GT R3 GT R4 GT R5 NIDLT Idle Channel Noise NIDLR AVT 1020 AVR PSRRT Noise Freq.: PSRRR 0 to 50 kHz Noise Level: 50 mVPP 0
A/LVFRO
Freq. (Hz) 0 to 60 1020 3300 3400 3968.75 0 to 3000 1020 3300 3400 3968.75
Level (dBm0)
Others
Min. 25 -0.15
Typ. -- -- Reference -- -- -- -- Reference -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reference -- -- -- -- Reference -- -- -- -- -- 0.320 0.320 -- --
Max. -- +0.20 +0.80 0.80 -- +0.20 +0.80 0.80 -- -- -- -- -- -- -- -- -- -- -- +0.2 +0.2 +0.5 +1.2 +0.2 +0.2 +0.5 +1.2 -68 (-75.7) -72 (-79.7) 0.359 0.359 -- --
Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dBm0p (dBmp)
LOSS T2 300 to 3000 0 --
-0.15 0 13 -0.15
0
--
-0.15 0 13
3 0 1020 -30 -40 -45 3 0 1020 -30 -40 -45 3 -10 1020 -40 -50 -55 3 -10 1020 -40 -50 -55 -- -- -- -- (*4) (*4) A/LGSX -- -- (*4) (*4)
35 35 35 28 23 35 35 35 28 23 -0.2 -0.2 -0.5 -1.2 -0.2 -0.2 -0.5 -1.2 -- -- 0.285 0.285 30 30
Absolute Signal Amplitude Power Supply Noise Rejection Ratio
Vrms Vrms dB dB
--
*4 P-message weighted filter used 0.320 Vrms = 0 dBm0 = -7.7 dBm
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Semiconductor Echo Canceler Characteristics
MSM7731-01
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Parameter Symbol Acoustic side Echo Attenuation Eres Line side (when CODEC or 16-bit linear data interface is used) Line side (m-law PCM used) Cancelable Echo Delay Time Tacoud Tacoud Tlined Single mode Dual mode (acoustic side) Dual mode (line side) -- -- -- -- 35 30 -- -- -- 59 27 ms ms 59-Tlined ms -- dB Condition Min. Typ. Max. Unit
Measurement System Block Diagram White noise generator L.P.F. 5kHz Analog MSM7731 Analog RIN ROUT Delay Echo delay time TD
Line or Acoustic EC Level meter Analog SOUT SIN Analog
ATT E.R.L (echo return loss)
Power supply voltage 3V CODEC input gain = 1 CODEC output gain = 1
Noise Canceler Characteristics
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Parameter Noise Attenuation Symbol Nres Condition White noise, voice band Min. -- Typ. 13 Max. -- Unit dB
Measurement System Block Diagram White noise generator L.P.F. 5kHz Analog AIN NC LOUT MSM7731 Analog Level meter
Power supply voltage 3V CODEC input gain = 1 CODEC output gain = 1
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Semiconductor
MSM7731-01
TIMING DIAGRAM
Power-down Reset Timing
PDN/RST pin tRSTW
PDN/RST control bit tPDND Internal operation PCMO, PCMEO DOUT Power-down tPDNH Initial mode
Hi-Z
Power-down Reset Setting Timing
SYNC (External clock)
BCLK (External clock) tPDNS PDN/RST control bit (Internal write)
Control Timing
tPARW Pin/control bit tPARD Internal operation tPARH Internal processing
Note: Applies to the following pins/control bits: LINEEN, SLPTHR, NCTHR, GLPADTHR, TPAD6-1, RPAD6-1, RST, ATHR, AATT, AHLD, AHD, AGC, LTHR, LATT, LHLD, LHD, and LGC
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Semiconductor Digital Input Timing (Normal-sync)
BCLK 0
tBS
MSM7731-01
1
tSB
2
tWS
3
4
5
6
7
8
9
10
SYNC
tDS tDH
PCMI PCMEI
MSB
LSB
Digital Input Timing (Short-frame-sync)
BCLK 0
tBS
1
tSB
2
tWS
3
4
5
6
7
8
9
10
SYNC
tDS tDH
PCMI PCMEI
MSB
LSB
Digital Output Timing (Normal-sync)
BCLK
0
tBS
1
tSB
2
tWS
3
4
5
6
7
8
9
10
SYNC PCMO PCMEO
tSDX
tXD1
tXD2
tXD3
MSB
LSB
Hi-Z
Hi-Z
Digital Output Timing (Short-frame-sync)
BCLK
0
tBS
1
tSB
2
tWS
3
4
5
6
7
8
9
10
SYNC PCMO PCMEO
tXD1
tXD2
tXD3
MSB
LSB
Hi-Z
Hi-Z
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Semiconductor
DEN
tM9 tM4 tM11
Microcomputer Interface I/O Timing
tM1
EXCK 3 4 5 6 7 8 9 10 11 12 13
1
2
14
15
16
tM2 tM5 tM6
tM3
DIN
tM7 tM8
W/R
A6
A5
A4
A3
A2
A1
A0
B7
B6
B5
B4
B3
B2
B1
B0
tM10
DOUT
B7
B6
B5
B4
B3
B2
B1
B0
MSM7731-01
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Semiconductor Rin input level vs. echo attenuation (Measuring conditions) Rin signal E.R.L Delay time ATT, GC Noise floor : : : : : 5 kHz band white noise -6dB 4ms OFF -60dBm (P-message filter unused)
MSM7731-01
RIN input level vs. echo attenuation 45 40 35
Echo attenuation [dB]
30 25 20 15 10 5 0 -50 -45 -40 -35 -30 -25 -20 -15 -10
Rin input level [dBm]
E.R.L. level vs. echo attenuation (with GLPAD) (Measuring conditions) Rin signal : 5 kHz band white noise Rin input level : -20dBm (with GLPAD=0dB) : -26dBm (with GLPAD=6dB) : -32dBm (with GLPAD=12dB) : -38dBm (with GLPAD=18dB) Delay time : 4ms ATT, GC : OFF Noise floor : -60dBm (P-message filter unused)
E.R.L vs. echo attenuation (with GLPAD) 45 40 35
Echo attenuation [dB]
GLPAD=0dB GLPAD=6dB GLPAD=12dB GLPAD=18dB
30 25 20 15 10 5 0 -40 -35
-30
-25
-20
-15
-10 E.R.L. [dB]
-5
0
5
10
15
20
25
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Semiconductor
MSM7731-01
Echo delay time vs. echo attenuation (Dual echo canceler mode/acoustic side) (Measuring conditions) Rin signal Rin input level E.R.L ATT, GC Noise floor : : : : : 5 kHz band white noise -16dBm -6dB OFF -60dBm (P-message filter unused)
Echo delay time vs. echo attenuation Dual echo canceler mode (acoustic side) 45 40 35
Echo attenuation [dB]
30 25 20 15 10 5 0 5 10 15 20 25 30 35 Echo delay time [ms] 40 45 50 55 60
Echo delay time vs. echo attenuation (Dual echo canceler mode/line side) (Measuring conditions) Rin signal Rin input level E.R.L ATT, GC Noise floor : : : : : 5 kHz band white noise -16dBm -6dB OFF -60dBm (P-message filter unused)
Echo delay time vs. echo attenuation Dual echo canceler mode (line side) 45 40 35
Echo attenuation [dB]
30 25 20 15 10 5 0 5 10 15 20 25 30 35 Echo delay time [ms] 40 45 50 55 60
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Semiconductor Echo delay time vs. echo attenuation (Single echo canceler mode) (Measuring conditions) Rin signal Rin input level E.R.L ATT, GC Noise floor : : : : : 5 kHz band white noise -16dBm -6dB OFF -60dBm (P-message filter unused)
MSM7731-01
Echo delay time vs. echo attenuation Single echo canceler mode 45 40 35
Echo attenuation [dB]
30 25 20 15 10 5 0 5 10 15 20 25 30 35 Echo delay time [ms] 40 45 50 55 60
Slope filter frequency characteristic (with CODEC frequency characteristic) (Measuring conditions) Rin input level : -16dBm Noise floor : -60dBm (P-message filter unused)
Slope filter frequency characteristic 10 0 -10
Gain [dB]
-20 -30 -40 -50 -60 1 501 1001 1501 2001 2501 3001 3501
Frequency [Hz]
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Semiconductor
MSM7731-01
Echo Canceler Characteristics Data 1 (Line Echo, White Noise) (Measuring conditions) Rin signal Rin input level E.R.L ATT, GC Noise floor Echo attenuation=40dB : : : : : 5 kHz band white noise -20dBm 0dB OFF -60dBm (P-message filter unused)
Echo Canceler Characteristics Data 2 (Line Echo, Voice) (Measuring conditions) Rin signal Rin input level E.R.L ATT, GC Noise floor Echo attenuation=34dB : : : : : Voice about -20dBm 0dB OFF -60dBm (P-message filter unused)
Echo Canceler Characteristics Data 3 (Acoustic Echo, Voice) (Measuring conditions) Rin signal : Rin input level : Speaker output level : Distance from microphone and speaker : GC : ATT, Noise Canceller : Noise floor : Echo attenuation=34dB Measurement System Block Diagram (Acoustic Echo)
3V R7 100 C9 10 EC SOUT SIN AIN AGSX R9 22k RV1 C10 734 1 + R8 2.2k J1 MIC
Voice about -20dBm 80dBa (at 1m) 5cm OFF ON -60dBm (P-message filter unused)
M7731
MIC
RIN
ROUT
AVFRO R13 22k APWI R14 22k R15 1.2k RV4 10k 5V U13 LM4861 1 8 2 7 3 6 4 5 R17 470k C15 10p AG AG
AOUT
R16 10k C13 0.1 C14 0.1
J3 SP SP
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Semiconductor
MSM7731-01
FUNCTIONAL DESCRIPTION
Control Registers
Table 2 Control Register Map
Reg Address B7 B6 *RST -- -- -- -- -- A14 A6 D14 D6 B5 Contents B4 B3 B2 B1 OPE B0 OPE *LINEEN CLKEN -- RPAD6 TPAD6 -- -- A13 A5 D13 D5 -- RPAD5 TPAD5 *LHD *AHD A12 A4 D12 D4 PCMEN PCMEEN -- RPAD4 TPAD4 LCLP ACLP A11 A3 D11 D3 R/W R/W
Name A6 A5 A4 A3 A2 A1 A0
CR0 0 0 0 0 0 0 0 *PDN/RST CR1 0 0 0 0 0 0 1 CR2 0 0 0 0 0 1 0 CR3 0 0 0 0 0 1 1 CR4 0 0 0 0 1 0 0 CR5 0 0 0 0 1 0 1 CR6 0 0 0 0 1 1 0 CR7 0 0 0 0 1 1 1 CR8 0 0 0 1 0 0 0 CR9 0 0 0 1 0 0 1 DMWR -- -- *LTHR *ATHR A15 A7 D15 D7
*MCUSEL *ECSEL
*GLPADTHR *SLPTHR *NCTHR R/W
RPAD3 TPAD3 *LHLD *AHLD A10 A2 D10 D2
RPAD2 TPAD2 *LATT *AATT A9 A1 D9 D1
RPAD1 R/W TPAD1 R/W *LGC *AGC A8 A0 D8 D0 R/W R/W R/W R/W R/W R/W
CR10 0 0 0 1 0 1 0 GPADA2 GPADA1 LPADA2 LPADA1 GPADL2 GPADL1 LPADL2 LPADL1 R/W CR11 0 0 0 1 0 1 1 CR12 0 0 0 1 1 0 0 READY -- -- -- -- -- -- -- -- -- -- -- PCMSEL SYPDN R/W -- -- R/W
*: Shared control bit with port (pin) --: Reserved bit. Do not change the initial value ("0").
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Semiconductor (1) CR0 (basic operating mode settings)
B7 CR0 Initial value (*4) PDN/RST 0 B6 RST 0 B5 LINEEN 0 B4 CLKEN 0 B3 PCMEN 0 B2 PCMEEN 0
MSM7731-01
B1 OPE MCUSEL 0
B0 OPE ECSEL 0
Note: *4. Initial values are the values set when reset is activated by the PDN/ RST pin. (Initial values are also set in the same manner, except for CR0-B7, when reset by the PDN/RST bit of B7).
B7 .......... Power-down reset 0: power-on, 1: power-down reset During power-down reset, this device enters the power-down state. At this time, all control register bits and internal variables are reset. After power-down reset is released, this device enters the initial mode. This bit is internally ORed with the inverted PDN/RST signal. B6 .......... Reset control 0: normal operation, 1: reset At reset, the coefficients for the echo canceler and noise canceler are reset. Control register contents are preserved. While reset is being processed, there is no sound. Use this bit in cases where the echo path changes (due to line switching during a telephone conversation, etc.), or when resuming telephone communicaion. This bit is internally ORed with the inverted RST signal. B5 .......... Line CODEC I/O control 0: ON, 1: OFF When OFF, the line CODEC is in the power-down state, the line CODEC output pin is at high impedance and line CODEC input pin is internally processed as an idle pattern input. This bit is internally ORed with the LINEEN pin. When the line CODEC is not used, this control results in low consumption of electrical power. This bit can only be set to "0" or "1" during power-down reset and the initial mode. B4 .......... SYNC, BCLK output control 0: ON, 1: OFF When OFF, the SYNC and BCLK output pins are in the high impedance state. This control is valid when the CLKSEL pin is at a logic "0" and has selected the internal clock mode. When the SYNC and BCLK clocks are not used externally, this control results in low consumption of electrical power. This bit can only be set to "0" or "1" during power-down reset and the initial mode. B3 .......... PCM I/O control 0: ON, 1: OFF When OFF, the PCMO output pin is in the high impedance state and the PCMI input pin is internally processed as an idle pattern input. When the line digital interface is not used, this control results in low consumption of electrical power. This bit can only be set to "0" or "1" during power-down reset and the initial mode. B2 .......... PCME I/O control 0: ON, 1: OFF When OFF, the PCMEO output pin is in the high impedance state and the PCMEI input pin is internally processed as an idle pattern input. When not used for message output and memo recording, this control results in low consumption of electrical power. This bit can only be set to "0" or "1" during power-down reset and the initial mode. 28/43
Semiconductor
MSM7731-01
B1, B0 ... Operating mode selection (0, 0): Initial mode Approximately 200 ms after power-down reset is released, the initial mode is entered. Only in this mode can the contents of the internal default value store memory be modified and CR0-B5 to CR0-B0, CR1-B7, CR11-B1 and CR11-B0 be set. In this mode, digital signal output pins are at high impedance, digital communication input pins are internally processed as idle pattern inputs, and neither the echo canceler nor the noise canceler operates. This mode is skipped when the MCUSEL pin is "1". This mode is released by setting the modes shown below. Refer to the flowchart of Figure 5. (1, 0): Dual echo canceler mode The acoustic echo canceler, line echo canceler and other functions can be operated by control from the control registers. Refer to Figure 6. The initial setting for cancelable echo delay time is as follows: Acoustic delay time (Tacoud) = 44 ms Line delay time (Tlined) = 15 ms (1, 1): Single echo canceler mode The acoustic echo canceler and other functions can be operated by control from the control registers. Control of the line echo canceler is unnecessary in this mode. Refer to Figure 7. (Other): Reserved bit (cannot be used) Note: The MCUSEL pin is internally ORed with B1, and the ECSEL pin is internally ORed with B0. To return to the initial mode after it has been released, activate power-down reset.
Power-down reset Power-down state Power-down reset release Wait for 200 ms * Control registers are reset * Internal variables are reset Initial mode
Note: During the initial mode, the READY bit (CR11-B7) is "1", at all other times it is "0".
Acoustic CODEC
Acoustic Echo Canceler
Noise Canceler
Slope Filter
Line Echo Canceler
Line CODEC
Set control register
Figure 6 Dual Echo Canceler Mode
Modify default store memory
CR0-B1=1 YES
NO
Acoustic CODEC Acoustic Echo Canceler Line CODEC
Start normal operation
Noise Canceler
Slope Filter
Figure 5 Initial Mode Flowchart
Figure 7 Single Echo Canceler Mode
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Semiconductor (2) CR1
B7 CR1 Initial value DMWR 0 B6 -- 0 B5 -- 0 B4 -- 0 B3 -- 0 B2
MSM7731-01
B1
B0 NCTHR 0
GLPADTHR SLPTHR 0 0
B7 .......... Internal data memory write control 0: write inhibited, 1: write In internal data memory, the data set in CR8 (D15 to D8) and CR9 (D7 to D0) is written to the memory address set in CR6 (A15 to A8) and CR7 (A7 to A0). Writing is possible only during the initial mode. For further details, refer to the internal data memory access method. B6, B5, B4, B3 .. Reserved bits Modification of initial values is inhibited B2 .......... Echo canceler I/O PAD control 0: "through mode", 1: normal mode This bit controls the attenuators (LPADL/A) provided in the SinL/A inputs and the amplifiers (GPADL/A) provided in the SoutL/A outptus of the echo canceler. Levels are set by the CR10 register. Use this bit when the echo return loss (value of returned echo) is amplified. This bit is internally ORed with the GLPADTHR pin. B1 .......... Slope filter control 0: normal mode (slope filter operation), 1: "through mode" This bit controls operation of the transmit slope filter. In the "through mode", the filter is halted and data is output directly. This bit is internally ORed with the SLPTHR pin. B0 .......... Noise canceler control 0: normal mode (noise canceler operation), 1: "through mode" This bit controls operation of the noise canceler. In the "through mode", the noise canceler is halted and data is output directly. This bit is internally ORed with the NCTHR pin. If this bit is changed to the normal mode, approximately 20 ms of data dropout will occur.
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Semiconductor (3) CR2 (Receive side level control)
B7 CR2 Initial value -- 0 B6 -- 0 B5 RPAD6 0 B4 RPAD5 0 B3 RPAD4 0 B2 RPAD3 0
MSM7731-01
B1 RPAD2 0
B0 RPAD1 0
B7, B6 ... Reserved bits Modification of initial values is inhibited B5, B4, B3, B2, B1, B0 ...... Receive side level setting (RPAD) These bits adjust the receive signal gain and set the mute level. Notice that only the mute level setting differs from pin control. When using this register, set the RPAD4, 3, 2, 1 pins to a logic "0". (0, 0, 1, 0, 1, 0): (0, 0, 1, 0, 0, 1): (0, 0, 1, 0, 0, 0): (0, 0, 0, 1, 1, 1): (0, 0, 0, 1, 1, 0): (0, 0, 0, 1, 0, 1): (0, 0, 0, 1, 0, 0): (0, 0, 0, 0, 1, 1): (0, 0, 0, 0, 1, 0): (0, 0, 0, 0, 0, 1): (0, 0, 0, 0, 0, 0): (1, 1, 1, 1, 1, 1): (1, 1, 1, 1, 1, 0): (1, 1, 1, 1, 0, 1): (1, 1, 1, 1, 0, 0): (1, 1, 1, 0, 1, 1): (1, 1, 1, 0, 1, 0): (1, 1, 1, 0, 0, 1): (1, 1, 1, 0, 0, 0): (1, 1, 0, 1, 1, 1): (1, 1, 0, 1, 1, 0): (1, 1, 0, 1, 0, 1): (1, 1, 0, 1, 0, 0): (1, 1, 0, 0, 1, 1): (1, 1, 0, 0, 1, 0): (1, 1, 0, 0, 0, 1): (1, 1, 0, 0, 0, 0): (1, 0, 1, 1, 1, 1): (1, 0, 1, 1, 1, 0): (1, 0, 1, 1, 0, 1): (1, 0, 1, 1, 0, 0): (1, 0, 1, 0, 1, 1): 30 dB 27 dB 24 dB 21 dB 18 dB 15 dB 12 dB 9 dB 6 dB 3 dB 0 dB -3 dB -6 dB -9 dB -12 dB -15 dB -18 dB -21 dB -24 dB -27 dB -30 dB -33 dB -36 dB -39 dB -42 dB -45 dB -48 dB -51 dB -54 dB -57 dB -60 dB MUTE
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Semiconductor (4) CR3 (Transmit side level control)
B7 CR3 Initial value -- 0 B6 -- 0 B5 TPAD6 0 B4 TPAD5 0 B3 TPAD4 0 B2 TPAD3 0
MSM7731-01
B1 TPAD2 0
B0 TPAD1 0
B7, B6 ... Reserved bits Modification of initial values is inhibited B5, B4, B3, B2, B1, B0 ...... Transmit side level setting (TPAD) These bits adjust the transmit signal gain and set the mute level. Notice that only the mute level setting differs from pin control. When using this register, set the RPAD4, 3, 2, 1 pins to a logic "0". (0, 0, 1, 0, 1, 0): (0, 0, 1, 0, 0, 1): (0, 0, 1, 0, 0, 0): (0, 0, 0, 1, 1, 1): (0, 0, 0, 1, 1, 0): (0, 0, 0, 1, 0, 1): (0, 0, 0, 1, 0, 0): (0, 0, 0, 0, 1, 1): (0, 0, 0, 0, 1, 0): (0, 0, 0, 0, 0, 1): (0, 0, 0, 0, 0, 0): (1, 1, 1, 1, 1, 1): (1, 1, 1, 1, 1, 0): (1, 1, 1, 1, 0, 1): (1, 1, 1, 1, 0, 0): (1, 1, 1, 0, 1, 1): (1, 1, 1, 0, 1, 0): (1, 1, 1, 0, 0, 1): (1, 1, 1, 0, 0, 0): (1, 1, 0, 1, 1, 1): (1, 1, 0, 1, 1, 0): (1, 1, 0, 1, 0, 1): (1, 1, 0, 1, 0, 0): (1, 1, 0, 0, 1, 1): (1, 1, 0, 0, 1, 0): (1, 1, 0, 0, 0, 1): (1, 1, 0, 0, 0, 0): (1, 0, 1, 1, 1, 1): (1, 0, 1, 1, 1, 0): (1, 0, 1, 1, 0, 1): (1, 0, 1, 1, 0, 0): (1, 0, 1, 0, 1, 1): 30 dB 27 dB 24 dB 21 dB 18 dB 15 dB 12 dB 9 dB 6 dB 3 dB 0 dB -3 dB -6 dB -9 dB -12 dB -15 dB -18 dB -21 dB -24 dB -27 dB -30 dB -33 dB -36 dB -39 dB -42 dB -45 dB -48 dB -51 dB -54 dB -57 dB -60 dB MUTE
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Semiconductor (5) CR4 (Line echo canceler settings)
B7 CR4 Initial value LTHR 0 B6 -- 0 B5 -- 0 B4 LHD 0 B3 LCLP 0 B2 LHLD 0
MSM7731-01
B1 LATT 0
B0 LGC 0
B7 .......... "Through mode" control 1: "through mode", 0: normal mode (echo cnaceler operation) This is the "through mode" control bit for the line echo canceler. In the "through mode", RinL and SinL data is output directly to RoutL and SoutL respectively. Coefficients are not reset. This bit is internally ORed with the LTHR pin. B6, B5 ... Reserved bits Modification of initial values is inhibited B4 .......... Howling detector control 1: OFF, 0: ON This bit controls the function to detect and cancel the howling that occurs in an acoustic system such as a handsfree communication system. This bit is internally ORed with the LHD pin. B3 .......... Center clip control 1: ON, 0: OFF When the SoutL output of the line echo canceler is -57 dBm0 or less, the center clip function forcibly sets it to the minimum positive value. B2 .......... Coefficient update control 1: fixed coefficients, 0: updated coefficients This bit selects whether the adaptive FIR filter (AFR) coefficients for the line echo canceler will be updated. This bit is internally ORed with the LHLD pin. B1 .......... Attenuator control 1: ATT OFF, 0: ATT ON This bit turns ON or OFF the ATT function to prevent howling by means of attenuators (ATTsL, ATTrL) provided in the RinL input and SoutL output of the line echo canceler. If input is only to RinL, the ATT for SoutL (ATTsL) is activated. If input is only to SinL, or if there is input to both SinL and RinL, the ATT for RinL input (ATTrL) is activated. The ATT value of each attenuator is approximately 6 dB. This bit is internally ORed with the LATT pin. B0 .......... Gain controller 1: GC OFF, 0: GC ON This bit turns ON or OFF the gain control function to control the RinL input level and prevent howling by means of a gain controller (GainL) provided in the RinL input of the line echo canceler. The gain controller adjusts the RIN input level when it is -10 dBm0 or above, and it has the control range of 0 to -8.5 dB. This bit is internally ORed with the LGC pin.
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Semiconductor (6) CR5 (Acoustic echo canceler settings)
B7 CR5 Initial value ATHR 0 B6 -- 0 B5 -- 0 B4 AHD 0 B3 ACLP 0 B2 AHLD 0
MSM7731-01
B1 AATT 0
B0 AGC 0
B7 .......... "Through mode" control 1: "through mode", 0: normal mode (echo cnaceler operation) This is the "through mode" control bit for the acoustic echo canceler. In the "through mode", RinA and SinA data is output directly to RoutA and SoutA respectively. Coefficients are not reset. This bit is internally ORed with the ATHR pin. B6, B5 ... Reserved bits Modification of initial values is inhibited B4 .......... Howling detector control 1: OFF, 0: ON This bit controls the function to detect and cancel the howling that occurs in an acoustic system such as a handsfree communication system. This bit is internally ORed with the AHD pin. B3 .......... Center clip control 1: ON, 0: OFF When the SoutA output of the acoustic echo canceler is -57 dBm0 or less, the center clip function forcibly sets it to the minimum positive value. B2 .......... Coefficient update control 1: fixed coefficients, 0: updated coefficients This bit selects whether the adaptive FIR filter (AFR) coefficients for the acoustic echo canceler will be updated. This bit is internally ORed with the AHLD pin. B1 .......... Attenuator control 1: ATT OFF, 0: ATT ON This bit turns ON or OFF the ATT function to prevent howling by means of attenuators (ATTsA, ATTrA) provided in the RinA input and SoutA output of the acoustic echo canceler. If input is only to RinA, the ATT for SoutA (ATTsA) is activated. If input is only to SinA, or if there is input to both SinA and RinA, the ATT for RinA input (ATTrA) is activated. The ATT value of each attenuator is approximately 6 dB. This bit is internally ORed with the AATT pin. B0 .......... Gain controller 1: GC OFF, 0: GC ON This bit turns ON or OFF the gain control function to control the RinA input level and prevent howling by means of a gain controller (GainA) provided in the RinA input of the acoustic echo canceler. The gain controller adjusts the RIN input level when it is -10 dBm0 or above, and it has the control range of 0 to -8.5 dB. This bit is internally ORed with the AGC pin.
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Semiconductor (7) CR6 (Internal data memory write register)
B7 CR6 Initial value A15 0 B6 A14 0 B5 A13 0 B4 A12 0 B3 A11 0 B2 A10 0
MSM7731-01
B1 A9 0
B0 A8 0
B7 to B0 ....... Memory upper address control This register sets the upper address of memory. For the writing method, refer to the Method of Internal Data Memory Access section. (8) CR7 (Internal data memory write register)
B7 CR7 Initial value A7 0 B6 A6 0 B5 A5 0 B4 A4 0 B3 A3 0 B2 A2 0 B1 A1 0 B0 A0 0
B7 to B0 ....... Memory lower address control This register sets the lower address of memory. For the writing method, refer to the Method of Internal Data Memory Access section. (9) CR8 (Internal data memory write register)
B7 CR8 Initial value D15 0 B6 D14 0 B5 D13 0 B4 D12 0 B3 D11 0 B2 D10 0 B1 D9 0 B0 D8 0
B7 to B0 ....... Memory upper data control This register sets the memory's upper data. For the writing method, refer to the Method of Internal Data Memory Access section. (10) CR9 (Internal data memory write register)
B7 CR9 Initial value D7 0 B6 D6 0 B5 D5 0 B4 D4 0 B3 D3 0 B2 D2 0 B1 D1 0 B0 D0 0
B7 to B0 ....... Memory lower data control This register sets the memory's lower data. For the writing method, refer to the Method of Internal Data Memory Access section.
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Semiconductor (11) CR10 (Echo canceler I/O level settings)
B7 CR10 Initial value GPADA2 0 B6 GPADA1 0 B5 LPADA2 0 B4 LPADA1 0 B3 GPADL2 0 B2 GPADL1 0
MSM7731-01
B1 LPADL2 0
B0 LPADL1 0
B7, B6 ... Acoustic output level control These bits control the PAD level of the gain of the acoustic echo canceler's SoutA output. PAD is turned ON or OFF by either the GLPADTHR pin or the GLPADTHR control register bit (CR1-B2). It is recommended to set the level to the positive level equal to LPADA2 and LPADA1. (0, 1) : +18 dB (0, 0) : +12 dB (1, 1) : +6 dB (1, 0) : 0 dB B5, B4 ... Acoustic input level control These bits control the PAD level of the loss of the acoustic echo canceler's SinA input. PAD is turned ON or OFF by either the GLPADTHR pin or the GLPADTHR control register bit (CR1-B2). Set the level such that echo return loss (value of returned echo) will be attenuated. (0, 1) : - 18 dB (0, 0) : - 12 dB (1, 1) : - 6 dB (1, 0) : 0 dB B3, B2 ... Line output level control These bits control the PAD level of the gain of the line echo canceler's SoutL output. PAD is turned ON or OFF by either the GLPADTHR pin or the GLPADTHR control register bit (CR1-B2). It is recommended to set the level to the positive level equal to LPADL2 and LPADL1. (0, 1) : +18 dB (0, 0) : +12 dB (1, 1) : +6 dB (1, 0) : 0 dB B1, B0 ... Line input level control These bits control the PAD level of the loss of the line echo canceler's SinL output. PAD is turned ON or OFF by either the GLPADTHR pin or the GLPADTHR control register bit (CR1-B2). Set the level such that echo return loss (value of returned echo) will be attenuated. (0, 1) : - 18 dB (0, 0) : - 12 dB (1, 1) : - 6 dB (1, 0) : 0 dB
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Semiconductor (12) CR11 (SYNC power-down control register)
B7 CR11 Initial value READY 0 B6 -- 0 B5 -- 0 B4 -- 0 B3 -- 0 B2 -- 0
MSM7731-01
B1 PCMSEL 0
B0 SYPDN 0
B7 .......... Data write flag 1: write enabled, 0: write disabled After power-down reset is released, this device enters the initial mode. This bit becomes "1" only during the initial mode, enabling access to the internal data memory. Checking this bit will detect whether writing by an external microcomputer is possible. B6 to B2 ....... Reserved bits Modification of initial values is inhibited B1 .......... PCM coding format control 1: m-law PCM, 0: 16-bit linear This is the coding format selection bit for digital data communication. A logic "1" selects m-law PCM and a logic "0" selects 16-bit linear (2's complement) coding format. When an internal clock is selected, the BCLK signal determines the output clock frequency to be used when internal clock is selected. If the digital interface is not used, set this bit to logic "0" to select 16-bit linear coding format. Since this bit is ORed with the PCMSEL pin, set this bit to logic "0" when controlling by the pin. If this bit setting is changed, reset must be activated by either the PDN/RST pin or the PDN/RST bit (CR0-B7). B0 .......... SYNC power-down 1: SYNC power-down ON, 0: SYNC power-down OFF This bit turns ON or OFF the function that automatically enters the powerdown reset state when the SYNC signal is fixed to a logic "1" or "0". This function is valid when the external clock mode has been selected by the CLKSEL pin. If the SYNC signal is fixed at 8kHz or longer, this device automatically writes a logic "1" to the control register PDN/RST bit (CR0-B7) and enters the powerdown reset state. For timing details, refer to the electrical characteristics.
(13) CR12 (Reserved register)
B7 CR12 Initial value -- 0 B6 -- 0 B5 -- 0 B4 -- 0 B3 -- 0 B2 -- 0 B1 -- 0 B0 -- 0
B7 to B0 ....... Reserved bits
Modification of initial value is inhibited.
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Semiconductor
MSM7731-01
RELATIONSHIP BETWEEN PINS AND CONTROL REGISTERS
In this device, the same function is controlled by either a pin or a control retister. For example, when a function is controlled by a pin, setting of the corresponding control register is important. Table 3 shows the relationship between settings of pins when functions are controlled by control registers and settings of control registers when functions are controlled by pins. The setting value of a control register when a function is controlled by a pin is equal to its initial value when the device is reset by the PDN/RST pin or the PDN/RST bit (CR0-B7).
Table 3 Relationship between pins and control registers
Setting of pin when function is Setting of control register when controlled by control register Logic "0" Logic "1" Logic "0" Logic "0" Logic "0" Logic "0" Logic "0" Logic "0" Logic "0" Logic "0" Logic "0" Logic "0" Logic "1" Logic "0" Logic "0" Logic "0" function is controlled by pin 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Function LINEEN PDN/RST PCMSEL ECSEL LTHR/ATHR LHD/AHD LHLD/AHLD LATT/AATT LGC/AGC GLPADTHR NCTHR SLPTHR RST MCUSEL RPAD4-1 TPAD4-1
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Semiconductor Method of Internal Data Memory Access
MSM7731-01
So that the default values such as the cancelable echo delay time can be changed, contents of the memory that stores default values can be modified during the initial mode (CR0-B1, CR0-B0 = "00"). Refer to the procedure below. 1. Set the address of the default value store memory. (CR6, CR7) 2. Set the modified values (data). (CR8, CR9) 3. Set the write command. (CR1-B7 = "1") After the write operation is complete, the write command (CR1-B7) is cleared to "0". Consecutive writes are possible. Echo Canceler Delay Time Cancelable echo delay time is as follows. (1) Single echo canceler mode Acoustic echo canceler Default: 59 ms Variable range: 0.5 to 59 ms (in 0.5 ms steps) Line echo canceler operation is halted. (2) Dual echo canceler mode (operation of acoustic and line echo cancelers) Condition: acoustic delay time + line delay time 59 ms Acoustic echo canceler Default: 44 ms Variable range: 0.5 to 58.5 ms (in 0.5 ms steps) Line echo canceler Default: 15 ms Variable range: 0.5 to 27 ms (in 0.5 ms steps) Memory addresses are shown below. (1) Single echo canceler mode Memory address of acoustic echo canceler delay time: 009DH (2) Dual echo canceler mode Memory address of acoustic echo canceler delay time: 009BH Memory address of line echo canceler delay time: 009CH The method for calculating delay time is shown below. delay time [s] 8000 = delay time data (HEX) Example of 30 ms: 0.03 8000 = 240 (DEC) = 00F0 (HEX)
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Semiconductor Noise Attenuation
MSM7731-01
There is a trade-off between noise attenuation and sound quality. In other words, increasing the noise attenuation deteriorates sound quality, and decreasing the noise attenuation improves sound quality. The following three types of noise attenuation levels can be selected with this device. Noise attenuation approx. 13 dB (typ.) approx. 10 dB (typ.) approx. 9 dB (typ.) Sound quality Typ. Better than Type 1 Better than Type 2
Type 1 Type 2 Type 3
Note: Only type 1 is compatible with pin control. Memory address: 01C8H Data to be stored: Type 1 Type 2 Type 3 Data 2000H 3333H 4666H
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Semiconductor
MSM7731-01
NOTES ON USE
1. Use a stabilized power supply with a low level of noises (especially spike noises and pulse noises of high frequencies) in order to prevent this device from malfunction or degradation in characteristics. 2. Place a good characteristics of bypass-capacitor for the power supply near the pins of this device in order to assure its electrical characteristics. 3. Place a good characteristics of bypass-capacitor for the analog signal ground (SG pin) near the pins of this device in order to assure its electrical characteristics. 4. Connect the AGND, DGND1 and DGND2 to the system ground at a shortest distance and in a low impedance state. 5. Use a separate power supply for an external speaker amplifier so as not to be disturbed by externally generated noises. 6. When an external speaker amplifier is used, do gain adjusting without overflow (saturation) of speaker amplifier output. The overflow of speaker amplifier output decreases the echo attenuation. 7. Set the analog signal input level to less than 1.3VPP to prevent overflow. Otherwise, voice will be distorted. 8. Set the echo return loss (ERL) to be attenuated. If the echo return loss is to be amplified, the GLPAD function should be used. The ERL refers to echo attenuation (loss) between the echo canceler output (RoutA/RoutL) and the echo canceler input (SinA/SinL). Refer to Characteristics Diagram for the ERL vs. echo attenuation. 9. The input level should be -10 to -20dBm0. Refer to Characteristics Diagram for the RIN input level vs. echo attenuation. 10. Adjust the volume at the position of the echo canceler input (RinA/RinL). When in Dual Echo Canceler mode : Adjust the volume with TPAD and RPAD. When in Signal Echo Canceler mode : Adjust the volume with TPAD and RPAD, or with the analog input (LIN) that is set at less than 1.3VPP. 11. When the echo path is changed (when resuming telephone communication), reset the device with the PDN/RST pin or the PDN/RST bit. 12. After turning on the power, be sure to reset the device with PDN/RST pin or the PDN/RST bit. 13. In order to get the highest performance of this device, the following functions should be used. AATT/LATT : ON AGC/LGC : ON SLPTHR : Normal mode (slope filter operation) NCTHR : Normal mode (noise canceler operation) RPAD6-1 : Adjusting the volume of receive signal. TPAD6-1 : Adjusting the volume of transmit signal.
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Semiconductor
APPLICATION CIRCUIT
Microphone
MSM7731-01
NOISE CANCELER TPAD Rin AFF Rin RPAD PCMO PCMI PCMEO PCMEI MSM6679B Voice Recognition Processor cnt n P/S & S/P MCU I/F EC/NC/PAD control Sout + Sin A-inL Rout A-outL Sout SLOPE FILTER LINE ECHO CANCELER LINEAR CODEC
LINEAR CODEC
ACOUSTIC ECHO CANCELER
Analog or Digital
Speaker (8W)
A-inA
Sin
+
- AFF
A-outA
Rout
Speaker amplifier
Clock Gen
Timing Gen
X2
cnt 1
DEN EXCK DIN DOUT
MCK/X1
PDN/RST
SYNC SYNCSEL BCLK CLKSEL PCMSEL
Vocabulary Memory
MSM7731-01
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Semiconductor
MSM7731-01
PACKAGE DIMENSIONS
(Unit : mm)
QFP64-P-1414-0.80-BK
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.87 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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